81. JK Flip-Flop

How do you plan to solve it?

module jk_ff (
    input  CLK,
    input  J,
    input  K,
    output reg Q
);

    always@(posedge CLK )begin
        if(~J & ~K)begin
            Q <= Q;
        end

        else if(~J & K)begin
            Q <= 0;
        end

        else if(J & ~K)begin
            Q <= 1;
        end

        else if(J & K)begin
            Q <= ~Q;
        end

    end

endmodule