81. JK Flip-Flop

How do you plan to solve it?

module jk_ff (
    input  CLK,
    input  J,
    input  K,
    output reg Q
);
// Write your code here
    wire [1:0]a =({J,K});
    always@(posedge CLK)begin
        case(a)
            2'b00: Q <= Q;       // hold
            2'b01: Q <= 1'b0;    // reset
            2'b10: Q <= 1'b1;    // set
            2'b11: Q <= ~Q;  
        endcase
    end 
endmodule