How do you plan to solve it?
module jk_ff ( input CLK, input J, input K, output reg Q ); always @(posedge CLK) begin case ({J, K}) // Hold 2'b00: Q <= Q; // Reset 2'b01: Q <= 1'b0; // Set 2'b10: Q <= 1'b1; // Toggle 2'b11: Q <= ~Q; endcase end endmodule