81. JK Flip-Flop

How do you plan to solve it?

module jk_ff (
    input  CLK,
    input  J,
    input  K,
    output reg Q
);

    always @(posedge CLK) begin
        if (!J) begin // J=0
            if (K) Q <= 0;
        end else begin // J=1
            if (K) Q <= ~Q;
            else Q <= 1'b1;
        end
    end

endmodule