81. JK Flip-Flop

How do you plan to solve it?

module jk_ff (
    input  CLK,
    input  J,
    input  K,
    output reg Q
);
    wire q1;
    assign q1 = J ? (K ? ~Q : 1) : (K ? 0 : Q);
    always @(posedge CLK or posedge J or posedge K)
        Q <= q1;

endmodule