89. Serial-In Parallel-Out Register

module sipo4 (
    input        CLK,
    input        RST,
    input        serial_in,
    output reg [3:0] Q
);
    always @(posedge CLK or posedge RST) begin
        if (RST)
            Q <= 4'b0000;
        else
            Q <= {serial_in, Q[3:1]};
    end
endmodule

💡Remember

• MSB-first means the newest serial bit lands in Q[3] each edge.
• Asynchronous reset forces a known state independent of the clock.