89. Serial-In Parallel-Out Register

How do you plan to solve it?

module sipo4 (
    input        CLK,
    input        RST,
    input        serial_in,
    output reg [3:0] Q
);
always @ (posedge CLK or posedge RST) begin
    if(RST) begin
        Q<=4'b0;
    end else begin
        Q<={serial_in,Q[3:1]};
    end
end    
endmodule