89. Serial-In Parallel-Out Register

November 9, 2025

Solving Approach

How do you plan to solve it?

Code

module sipo4 (
    input        CLK,
    input        RST,
    input        serial_in,
    output reg [3:0] Q
);
    // Write your code here
    always@(posedge CLK,posedge RST)begin
        if(RST)
          Q <= 4'd0;
        else
          Q <= {serial_in,Q[3:1]};
    end
    
endmodule

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