89. Serial-In Parallel-Out Register

How do you plan to solve it?

module sipo4 (
    input        CLK,
    input        RST,
    input        serial_in,
    output reg [3:0] Q
);

    // Asynchronous active-high reset
    always @(posedge CLK or posedge RST) begin
        if (RST)
            Q <= 4'b0000;
        else
            Q <= {serial_in, Q[3:1]};
    end

endmodule