89. Serial-In Parallel-Out Register

Just do it

module sipo4 (
    input        CLK,
    input        RST,
    input        serial_in,
    output reg [3:0] Q
);
    always @(posedge CLK, posedge RST) begin
        if (RST) begin
            Q[3:0] <= 3'd0;
        end else begin
            Q[3:0] <= {serial_in, Q[3:1]};
        end
    end
    
endmodule