10. Splitting Vector

module vector_splitter (
    input  [7:0] in_vec,
    output [3:0] out1,
    output [1:0] out2,
    output       out3,
    output       out4
);
    assign out1 = in_vec[7:4]; // upper 4 bits
    assign out2 = in_vec[3:2]; // next 2 bits
    assign out3 = in_vec[1];   // single bit
    assign out4 = in_vec[0];   // single bit
endmodule

💡Remember

• Part-select ([msb:lsb]) extracts contiguous slices of a vector.
• Bit-select ([i]) extracts a single bit.
• Be careful with index order — [3:2] keeps MSB-to-LSB order (bit 3 becomes out2[1], bit 2 becomes out2[0]).
• By default, Verilog treats vectors as [msb:lsb]; always check you are mapping the right indices.
• This exercise reinforces that outputs can be of different widths — a powerful feature in module design.