9. XOR Gate Using Basic Gates

Design a XOR gate (xor_gate) using basic gates (and_gate, or_gate, not_gate).

Requirements

Module name: xor_gate
Inputs: a, b (1-bit each)
Output: y (1-bit)

Notes

You must build xor_gate structurally by instantiating smaller gate modules (and_gate, or_gate, not_gate).
Do not use Verilog’s built-in ^ operator.
Use the Boolean equation for XOR: y=(a⋅b')+(a'⋅b)

Truth Table

a	b	y
0	0	0
0	1	1
1	0	1
1	1	0

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Testbench Code

`timescale 1ns/1ps

module tb_xor_gate;
    // Inputs
    reg a, b;
    // DUT output
    wire y;
    // Expected output
    reg expected_y;

    // Mismatch flag
    wire mismatch = (y !== expected_y);

    // Counters
    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // DUT
    xor_gate dut (.a(a), .b(b), .y(y));

    // VCD: only inputs, output, expected, mismatch
    initial begin
        $dumpfile("tb_xor_gate.vcd");
        $dumpvars(0,
            tb_xor_gate.a, tb_xor_gate.b,
            tb_xor_gate.y,
            tb_xor_gate.expected_y,
            tb_xor_gate.mismatch
        );
    end

    // Apply, check, and print ONE row (no duplicate driving)
    task run_and_show;
        input ta, tb_;
        begin
            a = ta; b = tb_;
            expected_y = ta ^ tb_;
            #1; // settle

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch)
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            else
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;

            $display("%b %b | %b | %b | %b", a, b, y, expected_y, mismatch);
        end
    endtask

    initial begin
        $display("a b | y | expected_y | mismatch");
        $display("--------------------------------");

        // Truth table — each case executed exactly once
        run_and_show(0,0);
        run_and_show(0,1);
        run_and_show(1,0);
        run_and_show(1,1);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule