10. Splitting Vector

How do you plan to solve it?

module vector_splitter (
    input  [7:0] in_vec,
    output reg   [3:0] out1,
    output reg [1:0] out2,
    output reg out3,
    output reg out4
);
    // TODO: Assign outputs using part-selects and bit-selects
always@(*)
begin
    
    out1[3:0]= in_vec[7:4];
    out2[1:0]=in_vec[3:2];
    out3=in_vec[1];
    out4=in_vec[0];
end
    
endmodule