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Splitting Vector

akash45placement
akash45placement

Solving Approach

How do you plan to solve it?

This design makes use of vector and bit indexing in Verilog to extract specific parts of an input vector. While no explicit masking operations are used, the process is conceptually similar to masking, as it involves isolating subsets of bits within a larger word.

 

Code

module vector_splitter (
    input  [7:0] in_vec,
    output [3:0] out1,
    output [1:0] out2,
    output       out3,
    output       out4
);
    // TODO: Assign outputs using part-selects and bit-selects
    assign out1 = in_vec[7:4];
    assign out2 = in_vec[3:2];
    assign out3 = in_vec[1];
    assign out4 = in_vec[0];

endmodule

 

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Testbench Code

`timescale 1ns/1ps

module tb_vector_splitter;
    // Input
    reg [7:0] in_vec;

    // DUT outputs
    wire [3:0] out1;
    wire [1:0] out2;
    wire       out3;
    wire       out4;

    // Expected outputs
    reg [3:0] expected_out1;
    reg [1:0] expected_out2;
    reg       expected_out3;
    reg       expected_out4;

    // Mismatch signal (true if any output mismatches expected)
    wire mismatch = (out1 !== expected_out1) ||
                    (out2 !== expected_out2) ||
                    (out3 !== expected_out3) ||
                    (out4 !== expected_out4);

    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // Instantiate DUT
    vector_splitter dut (
        .in_vec(in_vec),
        .out1(out1),
        .out2(out2),
        .out3(out3),
        .out4(out4)
    );

    // VCD dump
    initial begin
        $dumpfile("tb_vector_splitter.vcd");
        $dumpvars(0,
            tb_vector_splitter.in_vec,
            tb_vector_splitter.out1, tb_vector_splitter.out2, tb_vector_splitter.out3, tb_vector_splitter.out4,
            tb_vector_splitter.expected_out1, tb_vector_splitter.expected_out2, tb_vector_splitter.expected_out3, tb_vector_splitter.expected_out4,
            tb_vector_splitter.mismatch
        );
    end

    // Task to run one test
    task run_test;
        input [7:0] t_in;
        begin
            in_vec = t_in;

            // Expected outputs
            expected_out1 = t_in[7:4];
            expected_out2 = t_in[3:2];
            expected_out3 = t_in[1];
            expected_out4 = t_in[0];

            #1;
            TOTAL_TEST_CASES++;
            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES++;
            end else begin
                TOTAL_FAILED_TEST_CASES++;
                $display("FAILED: in_vec=%b | out1=%b out2=%b out3=%b out4=%b | expected=%b %b %b %b | mismatch=%b",
                          in_vec, out1, out2, out3, out4,
                          expected_out1, expected_out2, expected_out3, expected_out4, mismatch);
            end
        end
    endtask

    initial begin
        // Test cases
        run_test(8'b0000_0000);
        run_test(8'b1111_1111);
        run_test(8'b1101_0110); // tricky case from example
        run_test(8'b1010_1100);
        run_test(8'b0101_0011);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule