10. Splitting Vector

How do you plan to solve it?

This design makes use of vector and bit indexing in Verilog to extract specific parts of an input vector. While no explicit masking operations are used, the process is conceptually similar to masking, as it involves isolating subsets of bits within a larger word.

module vector_splitter (
    input  [7:0] in_vec,
    output [3:0] out1,
    output [1:0] out2,
    output       out3,
    output       out4
);
    // TODO: Assign outputs using part-selects and bit-selects
    assign out1 = in_vec[7:4];
    assign out2 = in_vec[3:2];
    assign out3 = in_vec[1];
    assign out4 = in_vec[0];

endmodule