84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
always@ (posedge CLK or posedge RST or posedge PRE) begin
    if(RST) begin
        Q<=0;
    end
    else if(PRE) begin
        Q<=(1);
    end
    else begin
        if(T) begin 
            Q<=(~Q);
        end
        else begin
            Q<=Q;
        end
    end
end
endmodule