84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
      always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)
            Q <= 1'b0;        // highest priority: async reset
        else if (PRE)
            Q <= 1'b1;        // next priority: async preset
        else if (T)
            Q <= ~Q;          // toggle on clock edge
        else
            Q <= Q;           // hold
    end

endmodule