84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    // Write your code here
    always @ (posedge CLK or posedge RST or posedge PRE) begin
        if(RST) Q <=0;
        else if(PRE) Q <=1;
        else Q <= T?~Q:Q;

    end
endmodule