84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    // Write your code here
    always @(posedge RST or posedge PRE or posedge CLK) begin
        if (RST) 
            Q <= 1'b0;
        else if (PRE)
            Q <= 1'b1;
        else 
            Q <= T ? ~Q : Q;
    end
    
endmodule