84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    // Write your code here
    always@(posedge CLK or posedge RST or posedge PRE) begin
        if(RST) begin
            Q <= 1'b0;
        end else if(PRE) begin
            Q <= 1'b1;
        end else if (T) begin
            Q <= ~Q;
        end
    end
    
endmodule