module t_ff_async_pr (
input CLK,
input RST,
input PRE,
input T,
output reg Q
);
// Write your code here
always@(posedge CLK, posedge RST, posedge PRE)
begin
if(RST==1)
begin
Q<=0;
end
else
if(PRE==1)
begin
Q<=1;
end
else
begin
if(T==1)
begin
Q<=~Q;
end
else
begin
Q<=Q;
end
end
end
endmodule