84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    // Write your code here
    always @(posedge CLK,posedge RST,posedge PRE)
    begin
        if(RST)
            Q<=1'b0;
        else if(PRE)
            Q<=1'b1;
        else begin
            case(T)
            1'b0 : Q<=Q;
            1'b1 : Q<=~Q;
            endcase
        end
    end
    
endmodule