module t_ff_async_pr (
input CLK,
input RST,
input PRE,
input T,
output reg Q
);
// Write your code here
always@(posedge CLK or posedge PRE or posedge RST)
if ( RST == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (T ==1)
Q <=~Q;
else Q <= Q;
endmodule