How do you plan to solve it?
module t_ff_async_pr ( input CLK, input RST, input PRE, input T, output reg Q ); always @(posedge CLK or posedge RST or posedge PRE) begin if (RST) Q <= 1'b0; // Reset else if (PRE) Q <= 1'b1; // Preset else if (T) Q <= ~Q; // Toggle end endmodule