How do you plan to solve it?
module t_ff_async_pr ( input CLK, input RST, input PRE, input T, output reg Q ); // Write your code here always @(posedge PRE, posedge RST, posedge CLK)begin if(RST) Q<=0; else if(PRE) Q<=1; else begin if(T) Q<=~Q; end end endmodule