84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    always @(posedge CLK or posedge RST or posedge PRE)
    begin
        if(RST == 1'b1)
            Q <= 1'b0;
        else if(PRE == 1'b1)
            Q <= 1'b1;
        else
        begin
            if(T == 1'b1)
                Q <= ~Q;
            else
             Q <= Q;
        end
    end
    
endmodule