84. T Flip-Flop with Asynchronous Preset and Reset

How do you plan to solve it?

module t_ff_async_pr (
    input  CLK,
    input  RST,
    input  PRE,
    input  T,
    output reg Q
);
    // Write your code here
    always @ (posedge CLK or posedge RST or posedge PRE) begin
        Q <= RST ? 1'b0 : ((PRE ? 1'b1 : (T ? !Q : Q)));
    end    
endmodule