83. T Flip-Flop

How do you plan to solve it?

module t_ff (
    input  CLK,
    input  T,
    output reg Q
);
// Write your code here

  always@(posedge CLK)begin
    case(T)
      1'b0: Q <= Q;
      1'b1: Q <= ~Q;
      default: Q <= Q;
    endcase
  end

endmodule