83. T Flip-Flop

How do you plan to solve it?

module t_ff (
    input  CLK,
    input  T,
    output reg Q
);
// Write your code here
    wire q1;
    assign q1 = ~Q;
    always @(posedge CLK or negedge T)
        if (!T)
            Q <= Q;
        else Q <= q1;
endmodule