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9. XOR Gate Using Basic Gates

module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    assign y = ~a;
endmodule

module xor_gate (
    input  a, b,
    output y
);
    wire nota, notb, t1, t2;

    not_gate n1 (.a(a), .y(nota));
    not_gate n2 (.a(b), .y(notb));

    and_gate a1 (.a(a),   .b(notb), .y(t1));
    and_gate a2 (.a(nota), .b(b),   .y(t2));

    or_gate o1 (.a(t1), .b(t2), .y(y));
endmodule

💡Remember

  • Structural modeling: Build circuits by wiring up smaller modules.
  • Hierarchy: xor_gate uses three types of submodules (not_gate, and_gate, or_gate).
  • Intermediate wires: Required to connect outputs of not_gate and and_gate into the final OR.
  • Instantiation style: Use named port mapping (.a(signal)), which is safer for readability.