How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire a_bar,b_bar,p_out_1 ,p_out_2;
not_gate not1(.a(a),.y(a_bar));
not_gate not2(.a(b),.y(b_bar));
and_gate and1(.a(a),.b(b_bar), .y(p_out_1));
and_gate and2(.a(a_bar),.b(b) ,.y(p_out_2));
or_gate or1(.a(p_out_1),.b(p_out_2),.y(y));
endmodule