9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = !a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota;
    wire notb;
    wire nota_b;
    wire notb_a;

    // TODO: instantiate required gates
    not_gate nota_ (.a(a), .y(nota));
    not_gate notb_ (.a(b), .y(notb));
    and_gate nota_and_b (.a(nota), .b(b), .y(nota_b));
    and_gate notb_and_a (.a(a), .b(notb), .y(notb_a));
    or_gate or_sum (.a(nota_b), .b(notb_a), .y(y)); 

endmodule