9. XOR Gate Using Basic Gates

How do you plan to solve it?

Called the individual modules with their own instantiations and did them in the end.

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1,w2,w3,w4,w5,w6;
    // TODO: instantiate required gates
    not_gate n1 (.a(a), .y(w1));
    and_gate a1 (.a(w1), .b(b), .y(w3));
    not_gate n2 (.a(b), .y(w2));
    and_gate a2 (.a(a), .b(w2), .y(w4));
    or_gate o1 (.a(w3), .b(w4), .y(y));
endmodule