9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a| b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire o1,o2,o3,o4;
    // TODO: instantiate required gates
    not_gate no1(b,o1);
    not_gate no2(a,o2);
    and_gate and1(a,o1,o3);
    and_gate and2(b,o2,o4);
    or_gate or1(o3,o4,y);
    
endmodule