9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y= a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire abar,bbar,w1,w2;

    // TODO: instantiate required gates
    not_gate g1(a,abar);
    not_gate g2(b,bbar);

    and_gate g3(a,bbar,w1);
    and_gate g4(abar,b,w2);

    or_gate g5(w1,w2,y);

endmodule