9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota,notb,and1,and2;

    // TODO: instantiate required gates
    not_gate m1(.a(a),.y(nota));
    not_gate m2(.a(b),.y(notb));
    and_gate m3(.a(a),.b(notb),.y(and1));
    and_gate m4(.a(nota),.b(b),.y(and2));
    or_gate m5(.a(and1),.b(and2),.y(y));
    

endmodule