9. XOR Gate Using Basic Gates

How do you plan to solve it?

module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y= a | b;

endmodule

module not_gate(input a, output y);
    assign y = ~a;

endmodule


module xor_gate (
    input  a, b,
    output y
);
    wire w1, w2, w3, w4;

    not_gate n1 (.a(a) , .y(w1));
    not_gate n2 (.a(b) , .y(w2));  

    and_gate a1 (.a(a),.b(w2),.y(w3));
    and_gate a2 (.a(b),.b(w1),.y(w4)); 

    or_gate o1(.a(w3), .b(w4) ,.y(y));


    

endmodule