9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y = ~ a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire w1,w2;
and_gate A1(.a(a),.b(~b),.y(w1));
and_gate A2(.a(~a),.b(b),.y(w2)); 
or_gate o1(.a(w1),.b(w2),.y(y));     // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule