How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a |b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire bnot,anot,one,two;
not_gate bn (.a(b),.y(bnot));
not_gate an (.a(a),.y(anot));
and_gate agate (.a(a),.b(bnot),.y(one));
and_gate bgate (.a(anot),.b(b),.y(two));
or_gate sum (.a(one),.b(two),.y(y));
endmodule