// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a & b;
endmodule
module not_gate(input a, output y);
assign y = !a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w1, w2, w3, w4;
not_gate not1(b, w1);
and_gate and1(a, w1, w2);
not_gate not2(a, w3);
and_gate and2(b, w3, w4);
assign y = w2 | w4;
endmodule