9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~ a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1, w2, notb, nota;
    // TODO: instantiate required gates

    not_gate not1(b, notb);
    and_gate and1(a, notb, w1);
    not_gate not2(a, nota);
    and_gate and2(nota, b, w2);
    assign y = w1 ^ w2;
endmodule