9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire b_bar, a_bar, a_b_bar, a_bar_b;
    // TODO: instantiate required gates
    not_gate not_dut_1(b, b_bar);
    not_gate not_dut_2(a, a_bar);
    and_gate and_dut_1(a,b_bar,a_b_bar);
    and_gate and_dut_2(a_bar,b,a_bar_b);
    or_gate or_dut(a_b_bar, a_bar_b, y);
    

endmodule