How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
// write code here for or gate
assign y = a | b;
endmodule
module not_gate(input a, output y);
// write code here for not gate
assign y = !a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire b1,a1,y1,y2;
not_gate n0(
.a(b),
.y(b1)
);
not_gate n1(
.a(a),
.y(a1)
);
and_gate n2(
.a(a1),
.b(b),
.y(y2)
);
and_gate n3(
.a (a),
.b (b1),
.y (y1)
);
or_gate n4(
.a(y1),
.b(y2),
.y(y)
);
endmodule