9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire negatea;
    wire negateb;
    wire and1;
    wire and2;
    // TODO: instantiate required gates
    not_gate negatemod1(a,negatea);
    not_gate negatemod2(b,negateb);
    and_gate andmod1(a,negateb,and1);
    and_gate andmod2(b,negatea,and2);
    or_gate ormod2(and1,and2,y);


endmodule