XOR Gate Using Basic Gates

Solving Approach

How do you plan to solve it?

 

The XOR gate is implemented by inverting both inputs, building the terms (a AND NOT b) and (b AND NOT a) using AND gates, and then combining these terms with an OR gate to produce the final XOR result.

Code

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = !a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_a;
    wire not_b;
    wire and_a_notb;
    wire and_b_nota;

    // TODO: instantiate required gates
    not_gate not_gate_a (a,not_a);
    not_gate not_gate_b (b,not_b);

    and_gate and_a_not_b (a, not_b, and_a_notb);
    and_gate and_b_not_a (b, not_a, and_b_nota);

    or_gate xor_out (and_b_nota,and_a_notb,y);

endmodule

 

Upvote
Downvote

Testbench Code

`timescale 1ns/1ps

module tb_xor_gate;
    // Inputs
    reg a, b;
    // DUT output
    wire y;
    // Expected output
    reg expected_y;

    // Mismatch flag
    wire mismatch = (y !== expected_y);

    // Counters
    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // DUT
    xor_gate dut (.a(a), .b(b), .y(y));

    // VCD: only inputs, output, expected, mismatch
    initial begin
        $dumpfile("tb_xor_gate.vcd");
        $dumpvars(0,
            tb_xor_gate.a, tb_xor_gate.b,
            tb_xor_gate.y,
            tb_xor_gate.expected_y,
            tb_xor_gate.mismatch
        );
    end

    // Apply, check, and print ONE row (no duplicate driving)
    task run_and_show;
        input ta, tb_;
        begin
            a = ta; b = tb_;
            expected_y = ta ^ tb_;
            #1; // settle

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch)
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            else
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;

            $display("%b %b | %b | %b | %b", a, b, y, expected_y, mismatch);
        end
    endtask

    initial begin
        $display("a b | y | expected_y | mismatch");
        $display("--------------------------------");

        // Truth table — each case executed exactly once
        run_and_show(0,0);
        run_and_show(0,1);
        run_and_show(1,0);
        run_and_show(1,1);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule