9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire b1, a1, ab1, ab2;
    // TODO: instantiate required gates
    not_gate n1(b,b1);
    not_gate n2(a,a1);
    and_gate and1(a,b1,ab1);
    and_gate and2(a1,b,ab2);
    or_gate o1(ab1,ab2,y);
endmodule