9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
wire[3:0] w;
wire z;
not_gate n1(.a(a),.y(w[0]));
not_gate n2(.a(b),.y(w[1]));
and_gate a1(.a(a),.b(w[1]),.y(w[2]));
and_gate a2(.a(b),.b(w[0]),.y(w[3]));
or_gate  o1(.a(w[2]),.b(w[3]),.y(y));

    // TODO: instantiate required gates

endmodule