9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y = a |  b ;
endmodule

module not_gate(input a, output y);
   assign y = ! a ;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires

    // TODO: instantiate required gates

    wire b_not  , a_not ;

    wire and_1 , and_2 ;


    not_gate n1 (a , a_not);
    not_gate n2 (b , b_not);

    and_gate a1 (a , b_not , and_1);
    and_gate a2 (b , a_not , and_2);

    or_gate o1 (and_1 , and_2 , y );



endmodule