9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
assign y = a||b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire exp1, exp2;
    // TODO: instantiate required gates
    and_gate first_exp(a,~b,exp1);
    and_gate second_exp(~a,b,exp2);
    or_gate third_exp(exp1,exp2,y);
endmodule