9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y = a | b;

endmodule

module not_gate(input a, output y);
   assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire x1, x2, bu_a, bu_b;
    // TODO: instantiate required gates
    not_gate buA(.a(a), .y(bu_a));
    not_gate buB (.a(b), .y(bu_b));
    and_gate tren(.a(a), .b(bu_b), .y(x1));
    and_gate duoi(.a(bu_a), .b(b), .y(x2));
    or_gate kq(.a(x1), .b(x2), .y(y));

endmodule