9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire [4:1] w;

    // TODO: instantiate required gates
    not_gate N0(a,w[1]);
    not_gate N1(b,w[2]);

    and_gate A0(w[1],b,w[3]);
    and_gate A1(w[2],a,w[4]);

    or_gate O(w[3],w[4],y);


endmodule